revision 2.1 jan. 2004 1 r0 201-STC62WV51216 very low pow er/voltage cmos sram 512k x 16 bit (single ce pin) the stc 62wv51216 is a high performance, very low power cmos static random access memory organized as 524,288 words by 16 bits and operates from a wide range of 2.4v to 5.5v supply voltage. advanced cmos technology and circuit techniques provide both high speed and low power features with a typical cmos standby current of 1.5ua at 3v/25 o c and maximum access time of 55ns at 3.0v/85 o c. easy memory expansion is provided by an active low chip enable (ce) ,active low output enable(oe) and three-state output drivers. t he STC62WV51216 h as a n au t omatic pow er dow n feature, reducing the power consumption significantly when chip is deselected. the STC62WV51216 is available in 48b bga and 44l tsop2 packages. ? description ? features ? block diagram ? product family ? pin configurations stc international limited . reserves the right to modify document contents without notice. STC62WV51216 1 5 lb oe a0 a1 a2 nc d8 ub a3 a4 ce d0 d9 d10 a5 a6 d1 d2 v ss d11 a17 a7 d3 v cc v cc d12 a16 d4 v ss d14 d13 a14 a 5 d5 d6 d15 nc . a12 a13 we d7 a8 a8 a9 a10 a11 nc 1 a b c d e f g h 1 234 6 vss ? wide vcc operation voltage : 2.4~5.5v ? very low power consumption : vcc = 3.0v c-grade: 30ma (@55ns) operating current i -grade: 31ma (@55ns) operating current c-grade: 24ma (@70ns) operating current i -grade: 25ma (@70ns) operating current 1.5ua (typ.) cmos standby current vcc = 5.0v c-grade: 75ma (@55ns) operating current i -grade: 76ma (@55ns) operating current c-grade: 60ma (@70ns) operating current i -grade: 61ma (@70ns) operating current 8.0ua (typ.) cmos standby current ? high speed access time : -55 55ns -70 70ns ? automatic power down when chip is deselected ? three state outputs and ttl compatible row decoder memory array 2048 x 4096 column i/o write driver sense amp column decoder data buffer output a9 a8 a7 data buffer input control vss vcc oe we ce d15 d0 a0 a13 a14 a15 a1 a2 16 16 16 16 16 256 4096 2048 22 a17 a16 a10 a12 a6 a11 a3 address input buffer a5 address input buffer . . . . ub . . . . lb a4 a18 48-ball csp top view stc ? fully static operation ? data retention supply voltage as low as 1.5v ? easy expansion with ce and oe options ? i/o configuration x8/x16 selectable by lb and ub pin power dissipation speed ( ns ) standby ( i ccsb1 , max ) operating ( i cc , max ) product family operating temperature vcc range vcc=3v vcc=5v vcc=3v vcc=5v pkg type STC62WV51216ec tsop2-44 STC62WV51216fc +0 o c to +70 o c 2.4v ~ 5.5v 55 / 70 5ua 55ua 24ma 60ma bga-48-0912 STC62WV51216ei tsop2-44 STC62WV51216fi -40 o c to +85 o c 2.4v ~ 5.5v 55 / 70 10ua 110ua 25ma 61ma bga-48-0912 70ns 70ns 55ns : 3.0~5.5v 70ns : 2.7~5.5v a4 a3 a2 a1 a0 ce dq0 dq1 dq2 dq3 vcc vss dq4 dq5 dq6 dq7 we a18 a17 a16 a15 a14 a5 a6 a7 oe ub lb dq15 dq14 dq13 dq12 vss vcc dq11 dq10 dq9 dq8 a8 a9 a10 a11 a12 a13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 STC62WV51216ec STC62WV51216ei .com .com .com
revision 2.1 jan. 2004 2 r0 201-STC62WV51216 name function a0-a18 address input these 19 address inputs select one of the 524,288 x 16-bit words in the ram. ce chip enable input we write enable input the write enable input is active low and controls read and write operations. with the chip selected, when we is high and oe is low, output data will be present on the dq pins; when we is low, the data present on the dq pins will be written into the selected memory location. oe output enable input the output enable input is active low. if the output enable is active while the chip is selected and the write enable is inactive, data will be present on the dq pins and they will be enabled. the dq pins will be in the high impedance state when oe is inactive. lb and ub data byte control input lower byte and upper byte data input/output control pins. d0 - d15 data input/output ports these 16 bi-directional ports are used to read data from or write data into the ram. vcc power supply vss ground ? truth table ? pin descriptions stc STC62WV51216 c in input capacitance v in =0v 10 pf c dq input/output capacitance v i/o =0v 12 pf range ambient temperature vcc commercial 0 o c to +70 o c 2.4v ~ 5.5v industrial -40 o c to +85 o c 2.4v ~ 5.5v ? absolute maximum ratings (1) ? operating range ? capacitance (1) (ta = 25 o c, f = 1.0 mhz) 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. this parameter is guaranteed and not 100% tested. symbol parameter rating units v term terminal voltage with respect to gnd -0.5 to vcc+0.5 v t bias temperature under bias -40 to +85 o c t stg storage temperature -60 to +150 o c p t power dissipation 1.0 w i out dc output current 20 ma symbol parameter conditions max. unit ce is active low. chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. the dq pins will be in the high impedance state when the device is deselected. mode ce we oe lb ub d0~d7 d8~d15 vcc current h x x x x high z high z i ccsb , i ccsb1 not selected (power down) x x x h h high z high z i ccsb , i ccsb1 output disabled l h h x x high z high z i cc l l dout dout i cc h l high z dout i cc read l h l l h dout high z i cc ll din din i cc hl x din i cc write l l x lh din x i cc l xx h h high z high z i cc .com .com .com .com
revision 2.1 jan. 2004 3 r0 201-STC62WV51216 ? dc electrical characteristics ( ta = -40 to + 85 o c ) stc STC62WV51216 ? low v cc data retention waveform ( ce controlled ) ce data retention mode vcc t cdr vcc t r v ih v ih vcc v dr 1.5v R R Q R R Q R R Q .com .com .com .com
revision 2.1 jan. 2004 4 r0 201-STC62WV51216 jedec parameter name parameter name description unit t avax t rc read cycle time 70 -- -- 55 -- -- ns t avqv t aa address access time -- -- 70 -- -- 55 ns t elqv t acs chip select access time (ce) -- -- 70 -- -- 55 ns t ba t ba data byte control access time (lb,ub) -- -- 35 -- -- 30 ns t glqv t oe output enable to output valid -- -- 35 -- -- 30 ns t elqx t clz chip select to output low z (ce) 10 -- -- 10 -- -- ns t be t be data byte control to output low z (lb,ub) 5 -- -- 5 -- -- ns t glqx t olz output enable to output in low z 5 -- -- 5 -- -- ns t ehqz t chz chip deselect to output in high z (ce) -- -- 35 -- -- 30 ns t bdo t bdo data byte control to output high z (lb,ub) -- -- 35 -- -- 30 ns t ghqz t ohz output disable to output in high z -- -- 30 -- -- 25 ns t axox t oh data hold from address change 10 -- -- 10 -- -- ns ? ac electrical characteristics ( ta = -40 to + 85 o c ) read cycle ? ac test conditions (test load and input/output reference) ? key to switching waveforms waveform inputs outputs must be steady may change from h to l don t care: any change permitted does not apply must be steady will be change from h to l change : state unknown center line is high impedance ?off ?state may change from l to h will be change from l to h , stc STC62WV51216 (1) 1. t ba is 35ns/30ns (@speed=70ns/55ns) with address toggle . t ba is 70ns/55ns (@speed=70ns/55ns) without address toggle . note : input pulse levels vcc / 0v input rise and fall times 1v/ns input and output timing reference level 0.5vcc output load c l = 30pf+1ttl c l = 100pf+1ttl min. typ. max. min. typ. max. vcc = 2.7~5.5v vcc = 3.0~5.5v cycle time : 70ns cycle time : 55ns .com .com .com .com
revision 2.1 jan. 2004 5 r0 201-STC62WV51216 stc STC62WV51216 notes: 1. we is high in read cycle. 2. device is continuously selected when ce = v il . 3. address valid prior to or coincident with ce transition low. 4. oe = v il . 5. the parameter is guaranteed but not 100% tested. ? switching waveforms (read cycle) read cycle1 (1,2,4) t rc t oh t aa d out address t oh read cycle2 (1,3,4) read cycle3 (1,4) t oh t rc t oe d out lb,ub ce oe address t clz (5) t acs t chz (1,5) t ohz (5) t olz t aa t bdo t ba t be t clz t chz (5) d out lb,ub ce (5) t ba t acs t be t bdo .com .com .com .com
revision 2.1 jan. 2004 6 r0 201-STC62WV51216 ? ac electrical characteristics ( ta = -40 to + 85 o c ) write cycle ? switching waveforms (write cycle) stc STC62WV51216 jedec parameter name parameter name description unit t avax t wc write cycle time 70 -- -- 55 -- -- ns t e1lwh t cw chip select to end of write 70 -- -- 55 -- -- ns t avwl t as address setup time 0----0---- ns t avwh t aw address valid to end of write 70 -- -- 55 -- -- ns t wlwh t wp write pulse width 35 -- -- 30 -- -- ns t whax t wr write recovery time (ce,we) 0 -- -- 0 -- -- ns t bw t bw date byte control to end of write (lb,ub) 30 -- -- 25 -- -- ns t wlqz t whz write to output in high z -- -- 30 -- -- 25 ns t dvwh t dw data to write time overlap 30 -- -- 25 -- -- ns t whdx t dh data hold from write time 0----0---- ns t ghqz t ohz output disable to output in high z -- -- 30 -- -- 25 ns t whox t ow end of write to output active 5 -- -- 5 -- -- ns write cycle1 (1) t wr t wc (3) t cw (11) t bw (2) t wp t aw t ohz (4,10) t as (3) t dh t dw d in d out we ce oe address (5) (5) lb,ub (1) 1. t bw is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; t bw is 70ns/55ns (@speed=70ns/55ns) without address toggle. note : min. typ. max. min. typ. max. vcc = 2.7~5.5v vcc = 3.0~5.5v cycle time : 55ns cycle time : 70ns .com .com .com .com
revision 2.1 jan. 2004 7 r0 201-STC62WV51216 stc STC62WV51216 notes: 1. we must be high during address transitions. 2. the internal write time of the memory is defined by the overlap of ce and we low. all signals must be active to initiate a write and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t wr is measured from the earlier of ce or we going high at the end of write cycle. 4. during this period, dq pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. if the ce low transition occurs simultaneously with the we low transitions or after the we transition, output remain in a high impedance state. 6. oe is continuously low (oe = v il ). 7. d out is the same phase of write data of this write cycle. 8. d out is the read data of next address. 9. if ce is low during this period, dq pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 10. the parameter is guaranteed but not 100% tested. 11. t cw is measured from the later of ce going low to the end of write. write cycle2 (1,6) t wc t cw (11) (2) t wp t aw t whz (4,10) t as t wr (3) t dh t dw d in d out we ce address t ow (7) (8) (8,9) lb,ub t bw (5) (5) .com .com .com .com
revision 2.1 jan. 2004 8 STC62WV51216 stc r0 201-STC62WV51216 ? ordering information ? package dimensions e0.1 3: symbol "n" is the number of solder balls. 1: controlling dimensions are in millimeters. 2: pin#1 dot marking by laser or pad print. n e d notes: 48 12.0 9.0 e1 d1 e 3.75 5.25 0.75 side view d0.1 d1 1.4 max. e e1 0.25 d 0.05 solder ball 0.35 d 0.05 view a 3.375 2.625 48 mini-bga (9mm x 12mm) d note: stc (stc international limited.) assumes no responsibility for t he application or use of a ny product or circuit described he rein. stc does not authorize its products for use as cr itical components in any application in which the failu re of the stc product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. STC62WV51216 x x y y grade c: +0 o c ~ +70 o c i: -40 o c ~ +85 o c speed 55: 55ns 70: 70ns pkg material -: normal g: green p: pb free package f :bga-48-0912 e :tsop2-44 .com .com .com .com
revision 2.1 jan. 2004 9 ? package dimensions (continued) tsop2-44 r0 201-STC62WV51216 STC62WV51216 stc .com .com .com
|
